The present invention relates generally to interconnect technology in integrated circuit fabrication, and more particularly, to an interconnect structure, a system, and a method for assessing the permeability of layer material within interconnect such as a diffusion barrier layer material at a via bottom for example.
Common components of a monolithic IC (integrated circuit) include interconnect structures such as metal lines for electrically connecting integrated circuit devices formed on a semiconductor substrate, as known to one of ordinary skill in the art of integrated circuit fabrication. A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
Thus far, aluminum has been prevalently used for metallization within integrated circuits. However, as the width of metal lines are scaled down to smaller submicron and even nanometer dimensions, aluminum metallization is more prone to electromigration failure. Electromigration failure, which may lead to open and extruded metal lines, is now a commonly recognized problem. Moreover, as dimensions of metal lines further decrease, metal line resistance increases substantially, and this increase in line resistance may adversely affect circuit performance.
Given the concerns of electromigration and line resistance with smaller metal lines and vias, copper is considered a more viable metal for smaller metallization dimensions. Copper has lower bulk resistivity and potentially higher electromigration tolerance than aluminum. Both the lower bulk resistivity and the higher electromigration tolerance improve circuit performance.
Unfortunately, copper is a mid-bandgap impurity in silicon, silicon dioxide, and other dielectric materials. Thus, copper may diffuse easily into these common integrated circuit materials to degrade the circuit performance of integrated circuits. To prevent such undesired diffusion of copper, a diffusion barrier layer material is deposited to surround the copper interconnect at the interface between the copper interconnect and the surrounding material, as known to one of ordinary skill in the art of integrated circuit fabrication.
As device dimensions including dimensions of the copper interconnect are further scaled down, the thickness of the diffusion barrier layer material surrounding the interconnect is minimized to in turn minimize the resistance of the interconnect. However, with such thinner diffusion barrier layer material surrounding the interconnect, the material of the interconnect may undesirably move through the thin diffusion barrier layer material due to electron wind force. Such flux divergence is especially prevalent with higher current density through the interconnect as dimensions of the interconnect are further scaled down.
Such an attribute of the diffusion barrier layer material surrounding an interconnect wherein material of the interconnect moves through the diffusion barrier layer material due to electron wind force is termed the xe2x80x9cpermeabilityxe2x80x9d of the diffusion barrier layer material that is said to be xe2x80x9cpermeablexe2x80x9d. The flux of material of the interconnect through the diffusion barrier layer material may lead to interconnect failure from formation of voids within the interconnect. Thus, the permeability of the diffusion barrier layer material is desired to be characterized.
FIG. 1 shows an interconnect test structure 100 of the prior art for characterizing electromigration failure of a test line 102. The test line 102 is comprised of copper for example, and in that case, the test line 102 is surrounded by a diffusion barrier layer material 104. The test line 102 is coupled to a first feeder line 106 by a first via 108, and the test line 102 is coupled to a second feeder line 110 by a second via 112. The first via 108 and the second via 112 are part of the dual damascene structure of the test line 102, and the diffusion barrier layer material 104 surrounds the first via 108 and the second via 112.
The first and second feeder lines 106 and 110 are comprised of copper for example, and in that case, the first and second feeder lines 106 and 110 are surrounded by diffusion barrier layer materials 114 and 116, respectively. The first feeder line 106 is coupled to a first test pad 118, and the second feeder line 110 is coupled to a second test pad 120. During characterization of the interconnect test structure 100 of the prior art, electrons flow from the first feeder line 106 through the test line 102 to the second feeder line 110 when current is applied to flow through the interconnect test structure 100 via the first and second test pads 118 and 120.
In the interconnect test structure 100 of the prior art, the width of the feeder lines 106 and 110 (i.e., the dimension of the lines 106 and 110 going into the drawing page of FIG. 1) is significantly larger (i.e., more than ten times larger for example) than the width of the test line 102 (i.e., the dimension of the test line 102 going into the drawing page of FIG. 1). Thus, even when the diffusion barrier layer material 104 at the interface of interest 122 between the first via 108 and the first feeder line 106 is significantly permeable, the effect of the flux of material of the first feeder line 106 through such diffusion barrier layer material 104 into the test line 102 is not noticeable because the volume of such flux of material of the first feeder line 106 through the diffusion barrier layer material 104 into the test line 102 is negligible compared to the total volume of the first feeder line 106.
However, the permeability of the diffusion barrier layer material is desired to be characterized because flux of material of the interconnect through the diffusion barrier layer material may lead to interconnect failure from formation of voids within the interconnect. Thus, a mechanism is desired for assessing the permeability of the diffusion barrier layer material within interconnect.
Accordingly, in a general aspect of the present invention, a novel interconnect test structure is formed to assess the permeability of layer material within interconnect.
In one embodiment of the present invention, an interconnect test structure for assessing electromigration permeability of a layer material within an interconnect includes a feeder line comprised of a conductive material and having a first current density, J1, and a first length, L1. In addition, the interconnect test structure includes a cathode line comprised of a conductive material and coupled to the feeder line, and the cathode line is a source of electrons flowing into the feeder line. Furthermore, the interconnect test structure includes a test line comprised of a conductive material and coupled to the feeder line and having a second current density, L2, and a second length, L2, and the test line is a sink of electrons flowing from the feeder line. Additionally, the interconnect test structure includes a no-flux structure disposed between the cathode line and the feeder line. The layer material is disposed between the feeder line and the test line.
A product of the first current density and the first length of the feeder line, J1*L1, is less than a critical Blech length constant, (J*L)CRIT1 for the feeder line. In addition, a product of the second current density and the second length of the test line, J2*L2, is greater than a critical Blech length constant, (J*L)CRIT2 for the test line. An occurrence of a void within the feeder line indicates that the layer material is permeable, and an occurrence of a void within the test line indicates that the layer material is impermeable.
In another embodiment of the present invention, the layer material is disposed at a bottom of a via disposed between the feeder line and the test line that are fabricated as two separate interconnect levels, and the via is part of a dual damascene structure for the test line. In that case, an occurrence of a void within the via indicates that the layer material is impermeable. Alternatively, the layer material is disposed at a bottom of a via disposed between the feeder line and the test line that are fabricated as two separate interconnect levels, and the via is part of a dual damascene structure for the feeder line.
In a further embodiment of the present invention, a plurality of such interconnect test structures are formed, with each interconnect test structure having a respective feeder line with a respective width such that the widths of the respective feeder lines of the plurality of the interconnect test structure successively increases. A critical width of the respective feeder line of one of the plurality of the interconnect test structures is determined when a respective void therein transitions from occurring within the feeder line to occurring within the test line. This critical width indicates a level of permeability of the layer material.
In this manner, the interconnect test structure of the present invention determines whether or not the layer material within the interconnect is permeable. In addition, the level of permeability of the layer material is also determined. Such an interconnect test structure may advantageously be used for assessing the permeability of a diffusion barrier material within interconnect. The permeability of a diffusion barrier layer material within an interconnect results in electromigration failure of the interconnect structure, especially as the barrier material becomes thinner as integrated circuit device dimensions are further scaled down. The interconnect test structure of the present invention may advantageously be used for characterizing the level of such permeability for various thicknesses of the barrier layer material and for various types of the barrier layer material to design for minimized electromigration failure of interconnect structures having a diffusion barrier layer material.
These and other features and advantages of the present invention will be better understood by considering the following detailed description of the invention which is presented with the attached drawings.